Andrew C Brown, III
Nursing at Springside Dr, Colorado Springs, CO

6804737, Oct 12, 2004

Dec 26, 2000

09/748324

Andrew Carl Brown - Colorado Springs CO
Russell Andrew Johnson - Monument CO

LSI Logic Corporation - Milpitas CA

G06F 1300

710240, 710305, 710300, 709208

An intelligent host adapter for coupling a host PC to peripheral I/O devices through I/O channels wherein the host adapter has a master/slave architecture. A master I/O processor includes circuits for coupling the host adapter to a slot in an I/O interface bus of the host PC such as a PCI bus. The master I/O processor also includes circuits for a relatively small fixed number of I/O channels for connection to associated I/O peripheral busses such as SCSI, Fiber Channel and networks (i. e. , Ethernet, token ring, etc. ). A slave I/O processor is coupled to the master I/O processor via a dedicated master/slave interface bus. The slave I/O processor provides for addition of I/O channels to the host adapter without requiring use of additional slots of the I/O interface bus of the host PC and without using associated I/O computing resources within the host PC.

6886147, Apr 26, 2005

Dec 31, 2002

10/335312

Gregory A. Johnson - Colorado Springs CO, US
Andrew Carl Brown - Colorado Springs CO, US
Travis Alister Bradfield - Colorado Springs CO, US

LSI Logic Corporation - Milpitas CA

G06F009/45

716 6, 716 5, 716 10

The present invention is a method, system, and product for optimizing timing in a circuit after layout of the circuit has been completed. The circuit includes at least one variable delay line and includes coupled endpoint devices. The variable delay line includes multiple, different selectable settings. A current setting of the variable delay line is varied from a maximum setting to a minimum setting. A timing accuracy indicator of a combination of the coupled endpoint devices is determined as the variable delay line is varied from its maximum setting to its minimum setting. Thus, multiple timing accuracy indicators are determined where an indicator is determined for and associated with each one of the settings from the maximum setting to the minimum setting. An optimum one of the selectable settings is determined utilizing the timing accuracy indicators, wherein the optimum one of the settings is associated with an optimum one of the multiple timing accuracy indicators.

6292855, Sep 18, 2001

Dec 18, 1998

9/217974

Russell A. Johnson - Colorado Springs CO
Andrew C. Brown - Colorado Springs CO
Stephen B. Johnson - Colorado Springs CO

LSI Logic Corporation - Milpitas CA

G06F 1210, G06F 1730

710 33

A set of registers are provided for a protocol engine driving I/O transactions requested by a host. A fixed set of defined data elements are determined for the protocol under which the I/O transaction is to be performed. Each register maps to a data structure base address or to a different data element offset or byte count. During initialization, the registers are programmed by an operating system device driver with offsets from a base address and byte counts for each data element within the defined set as those data elements are found within an operating system specific data structure for the I/O transaction, although data elements having a fixed size for each operating system may not require the byte count to be specified. For each I/O transaction requested, the base address in the host memory of the operating system specific data structure is programmed by the device driver into a register. The I/O protocol engine utilizes the base address together with the offset and byte count information to commence the requested I/O transaction.

6842792, Jan 11, 2005

Jun 27, 2002

10/183670

Stephen B. Johnson - Colorado Springs CO, US
Bradley D. Besmer - Colorado Springs CO, US
Guy W. Kendall - Colorado Springs CO, US
Christopher J. McCarty - Colorado Springs CO, US
Andrew C. Brown - Colorado Springs CO, US

LSI Logic Corporation - Milpitas CA

G06F 1314

710 5, 710 6, 709232, 711119

An apparatus comprising a plurality of IO queues and a logic circuit. The plurality of IO queues each may be configured to receive a respective IO request and present the IO request in response to a trigger signal. The logic circuit may be configured to (a) (i) receive one or more of the IO requests and (ii) serially coalesce the IO requests in response to a respective device identification (ID) of the IO requests, and (iii) present one or more of the coalesced IO requests as one or more respective context queue requests in response to the trigger signal and (b) generate the trigger signal when a current queue count is equal to a maximum queue depth.