Position:
Analog and Clock Systerm Designer at Intel
Work:
Intel
since Aug 2009
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Analog and Clock Systerm Designer
Intel
Oct 2005 - Sep 2009
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Engineering Manager
Hewlett-Packard
Aug 1997 - Feb 2005
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Design Engineer
Education:
Massachusetts Institute of Technology 1996 - 1997
MSEE, Electrical Engineering
Massachusetts Institute of Technology 1992 - 1996
BSEE, Electrical Engineering
Skills:
Hardware Design, SoC, Engineering Management, Processors, Analog Circuit Design, VLSI