ALLEN J CZAMARA
Broker in Auburn, MA
License number
Massachusetts 117430
Issued Date
Jun 12, 1989
Expiration Date
Dec 20, 2017
Type
Salesperson
Address
Address
Auburn, MA 01501
Professional information
Automatic Test Equipment With Pipelined Sequencer
US Patent:
5657486, Aug 12, 1997
Filed:
Dec 7, 1995
Appl. No.:
8/569020
Inventors:
Allen J. Czamara - Auburn MA
Romas P. Rudis - Westboro MA
Ernest P. Walker - Weston MA
Romas P. Rudis - Westboro MA
Ernest P. Walker - Weston MA
Assignee:
Teradyne, Inc. - Boston MA
International Classification:
G06F 900
US Classification:
395595
Abstract:
Automatic test equipment utilizing a pipelined sequencer to retrieve test vectors from a random access memory during execution of a test pattern. The order of execution of the test vectors need not be sequential and can be dynamically altered by conditions measured during execution of a test pattern. Though pipelined, the sequencer provides one vector per cycle, even if the execution order is dynamically altered. The sequencer, because it is pipelined, can be implemented with relatively low cost, though slower speed, components. The disclosed sequencer is implemented with CMOS components.
High Speed, Real-Time, State Interconnect For Automatic Test Equipment
US Patent:
6107818, Aug 22, 2000
Filed:
Apr 15, 1998
Appl. No.:
9/060987
Inventors:
Allen J. Czamara - Auburn MA
Assignee:
Teradyne, Inc. - Boston MA
International Classification:
G01R 3126, G01R 313181
US Classification:
324765
Abstract:
A tester is disclosed in which state coherency is maintained between functional blocks of the tester by way of a novel state distribution and recombination network. The network includes a plurality of nodes configured to provide point-to-point links between pairs of functional blocks. Further, time delays through the point-to-point links can be adjusted by selecting a suitable node configuration and by programming delay circuitry included in each node. The network therefore maintains state coherence between the functional blocks by ensuring that delays throughout the test system are both deterministic and adjustable. The tester is particularly useful for testing complex, mixed-signal semiconductor devices.
Test Ip-Based A.t.e. Instrument Architecture
US Patent:
2013022, Aug 29, 2013
Filed:
Jan 16, 2013
Appl. No.:
13/742589
Inventors:
Allen J. Czamara - Auburn MA, US
Ed Paulsen - Medway MA, US
Lev Alperovich - Lexington MA, US
Ed Paulsen - Medway MA, US
Lev Alperovich - Lexington MA, US
International Classification:
G01R 31/3177
US Classification:
714735
Abstract:
A test system based on multiple instances of reconfigurable instrument IP specifically matched to the device under test may be used in integrating automated testing of semiconductor devices between pre-silicon simulation, post-silicon validation, and production test phases, in one embodiment of software and hardware across all three phases, for different devices. The reconfigurable test system comprises: a tester instrument, instances of instrument IP instantiated in the tester instruments, a computer system, and a test program. The tester instrument connects to a device under test (DUT), and includes FPGAs reconfigurable for the three testing phases. The computer system has a user interface, and a controller connected to the reconfigurable tester instrument via a data bus. The test program stored on the controller, and the controller, instantiates interfaces and protocols, and certain process transactions to support the protocols, into FPGAs, to match device interfaces for each DUT, to execute test sequences.