ALBRIK AVANESSIAN
Broker in Watertown, MA
License number
Massachusetts 9523338
Issued Date
Apr 21, 2012
Expiration Date
Jul 2, 2014
Type
Salesperson
Address
Address
Watertown, MA 02472
Professional information
Albrik Avanessian - Watertown, MA
Work:
TJX, Inc
E-Commerce Project Coordinator Athenahealth, Inc - Watertown, MA
Technical Project Coordinator IBM Corp - Waltham, MA
Physical Design Team Engineer/Project Lead DIGITAL EQUIPMENT Corp - Maynard, MA
ASIC Physical Design Engineer
E-Commerce Project Coordinator Athenahealth, Inc - Watertown, MA
Technical Project Coordinator IBM Corp - Waltham, MA
Physical Design Team Engineer/Project Lead DIGITAL EQUIPMENT Corp - Maynard, MA
ASIC Physical Design Engineer
Education:
PMI
CAPM in Project Management Boston University
Certificate in Project Management Boston College
Graduate Certificate in Leadership for Change University of South Florida - Tampa, FL
B.S. in Computer Engineering University of South Florida - Tampa, FL
B.S. in Computer Science
CAPM in Project Management Boston University
Certificate in Project Management Boston College
Graduate Certificate in Leadership for Change University of South Florida - Tampa, FL
B.S. in Computer Engineering University of South Florida - Tampa, FL
B.S. in Computer Science
Intersect Area Based Ground Rule For Semiconductor Design
US Patent:
2009026, Oct 22, 2009
Filed:
Apr 18, 2008
Appl. No.:
12/105299
Inventors:
Albrik Avanessian - Watertown MA, US
Dureseti Chidambarrao - Weston CT, US
Stephen E. Greco - Lagrangeville NY, US
Douglas W. Kemerer - Essex Junction VT, US
Tina Wagner - Newburgh NY, US
Dureseti Chidambarrao - Weston CT, US
Stephen E. Greco - Lagrangeville NY, US
Douglas W. Kemerer - Essex Junction VT, US
Tina Wagner - Newburgh NY, US
Assignee:
INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY
International Classification:
G06F 17/50
US Classification:
716 5, 716 10
Abstract:
A design rule that determines a degree of overlap between two design elements in two adjoining levels by estimating a physical overlap area, or an “intersect area,” of corresponding structures in a semiconductor chip is provided. The estimation of the physical intersect area may factor in line edge biasing, critical dimension tolerance, overlay tolerance, and corner rounding to provide an accurate estimate of a physical area for each of the structures corresponding to the two design elements. The intersect area is employed as a metric to determine compliance with a ground rule, i.e., the ground rule is specified in terms of the intersect region. Other derived quantities such as electrical resistance, electromigration resistance, expected yield may be calculated from the intersect area, and may be advantageously employed to optimize the design data.