ALBERTO JOSE MARTINEZ
Pilots at Stratford Cir, Folsom, CA

6564330, May 13, 2003

Dec 23, 1999

09/472096

Alberto J. Martinez - El Dorado Hills CA
David I. Poisner - Folsom CA
Karthi R. Vadivelu - Fair Oaks CA

Intel Corporation - Santa Clara CA

G06F 126

713322

A wake up circuit for a computer system with a codec controller. The circuit provides a wakeup signal to the computer system when a codec detects an event that requires the system to become active. This signal is provided whether the communications link between the codecs and their controller is active or inactive. When the link is inactive, as indicated by the absence of a bit clock, a data signal on any of the codec input lines triggers the controller to send a power activation signal to the system and to initiate an activation of the codec link. If the link is already active, the general purpose input status change bit is transmitted to the controller, which writes it into a register that is used to trigger a power activation signal to the system. An enable input permits the wakeup signal to be enabled or disabled under program control. The wakeup signal can be used to trigger a system management interrupt or other interrupt suitable for initiating a system resume function.

6981081, Dec 27, 2005

Dec 19, 2002

10/325776

Alberto J. Martinez - El Dorado Hills CA, US
Christopher J. Spiegel - El Dorado Hills CA, US

Intel Corporation - Santa Clara CA

G06F013/14

710113, 710 44, 710 46, 710 47

A Bus Driver implements an arbitration mechanism to allow both the system management interrupt (SMI) and the Bus Driver to cooperatively use a Bus host controller hardware. This mechanism employs a hardware-based semaphore (status bit) to allow either the SMI or the driver to claim ownership of the Bus host controller for an arbitrary period of time. While either the SMI or the driver may own the status bit, the other party must poll the bit until ownership is achieved. For the SMI, this involves scheduling a periodic SMI interrupt. The driver performs self arbitration of claiming the status bit to provide the periodic SMI interrupt the opportunity to claim the bit. The mechanism allows the SMI access to the Bus host controller in a “timely” manner, while minimizing impact to driver access to the Bus host controller, which could impact driver Bus transaction throughput.

2005021, Sep 29, 2005

Mar 29, 2004

10/813537

Alberto Martinez - El Dorado Hills CA, US

G06F012/14

710022000, 711163000

Embodiments include a system for obfuscating the location of protected data in the memory of a computer system. The system provides a protected mode supported by a memory controller that does not allow the address relating to the location of protected data to be read or accessed. This system may be used to prevent the piracy of data temporarily stored in an unencrypted state in system memory.

6631429, Oct 7, 2003

Dec 23, 1999

09/471942

Erik C. Cota-Robles - Portland OR
Barry OMahony - Banks OR
Alberto J. Martinez - El Dorado Hills CA

Intel Corporation - Santa Clara CA

G06F 1300

710 52, 710 18, 710 53, 710 55, 710 56, 710 57, 710 61, 711744, 711775, 370235, 370360, 370394

In one embodiment of the present invention, an output device sends a spurious data sample in place of a first data sample to be sent from a queue if the queue is in a state of underflow during which the first data sample is not available to be sent. The buffer is to store data samples for an isochronous data transmission. Circuitry skips the first data sample when the first data sample becomes available in the queue so that synchronization for subsequent data samples sent from the queue is preserved. In another embodiment of the present invention, an input device advances an input buffer pointer to point to a next location in a memory in response to receiving a data sample at a queue during a state of overflow. The input buffer pointer indicates a location in the memory to which a next data sample is to be sent from the queue. The queue stores data samples for an isochronous data transmission.

7100032, Aug 29, 2006

Jun 28, 2002

10/187222

Jeffrey L. Rabe - Folsom CA, US
Alberto J. Martinez - El Dorado Hills CA, US
Serafin E. Garcia - Folsom CA, US
Jackie Wensel - Folsom CA, US

Intel Corporation - Santa Clara CA

G06F 9/00

713 1, 710 8, 719327

An approach to selecting either an actual stepping revision ID value or a compatible revision ID value to be readable by a processor through a revision ID register.

2005028, Dec 29, 2005

Jun 29, 2004

10/881076

Alberto Martinez - El Dorado Hills CA, US
James Chapple - Chandler AZ, US
Prashant Sethi - Folsom CA, US
Joseph Bennett - Roseville CA, US

G06F013/24

710260000

In some embodiments, the inventions include a chip having a status register circuit coupled to conductors to receive interrupt event signals to provide source signals corresponding to the interrupt event signals. The chip also includes a control register circuit to provide source enable signals for selective ones of the interrupt sources, and a re-arming logic circuit coupled to the conductors to receive the interrupt event signals and provide a re-arming signal. The chip further includes first logic circuit to receive the source signals, the source enable signals, and the re-arming signal to provide an initial interrupt signal, and message signaled interrupt (MSI) signal pulse generation logic to receive the initial interrupt signal and provide an MSI signal in response thereto. Other embodiments are described and claimed.

8538018, Sep 17, 2013

Jan 3, 2012

13/342288

Adeel A. Aslam - Davis CA, US
Alberto J. Martinez - El Dorado Hills CA, US
Ernie F. Brickell - Portland OR, US

Intel Corporation - Santa Clara CA

H04N 7/167

380237, 380236, 380201

Methods and apparatus for mixing encrypted data with unencrypted data are disclosed. A disclosed system receives data from a first media source, such as DVD-Audio content, and encrypts the data from the first media source using a key stream to form an encrypted data stream. The disclosed system may separate the encrypted data stream into a plurality of encrypted data streams and may combine the plurality of encrypted data streams with an unencrypted data stream associated with a second media source to form a mixed data stream. The mixed data stream is formed without decrypting the plurality of encrypted data streams and is transmitted to hardware or a hardware driver.

8219797, Jul 10, 2012

Dec 31, 2008

12/347879

Kumar Chinnaswamy - Hillsboro OR, US
Ittai Anati - Haifa, IL
Alberto Martinez - El Dorado Hills CA, US
Shay Gueron - Haifa, IL

Intel Corporation - Santa Clara CA

G06F 9/00, G06F 9/44, G06F 15/177

713100, 713 1, 717168, 717171, 717172, 717173, 717174, 717176, 717177, 717178

A method and system to allow the secure configuration of the configurable feature(s) of a hardware device in a platform. The configuration of the configurable feature(s) of the hardware device is performed with protection against software attacks. A management module determines that the platform is authorized to configure at least one configurable feature of the hardware device and configures each of the configurable feature(s) based on a received configuration message.

8098817, Jan 17, 2012

Dec 22, 2003

10/745424

Adeel A. Aslam - Davis CA, US
Alberto J. Martinez - El Dorado Hills CA, US
Ernie F. Brickell - Portland OR, US

Intel Corporation - Santa Clara CA

H04K 1/04

380 37, 380 42, 380200

Methods and apparatus for mixing encrypted data with unencrypted data are disclosed. A disclosed system receives data from a first media source, such as DVD-Audio content, and encrypts the data from the first media source using a key stream to form an encrypted data stream. The disclosed system may separate the encrypted data stream into a plurality of encrypted data streams and may combine the plurality of encrypted data streams with an unencrypted data stream associated with a second media source to form a mixed data stream. The mixed data stream is formed without decrypting the plurality of encrypted data streams and is transmitted to hardware or a hardware driver.

7571329, Aug 4, 2009

Jul 14, 2004

10/891699

Ernie F. Brickell - Portland OR, US
Alberto J. Martinez - El Dorado Hills CA, US
David W. Grawrock - Aloha OR, US
Clifford D. Hall - Orangevale CA, US

Intel Corporation - Santa Clara CA

G06F 12/14, G06F 11/30

713193, 713167

Secure storage and retrieval of a unique value associated with a device to/from a memory of a processing system. In at least one embodiment, the device needs to be able to access the unique value across processing system resets, and the device does not have sufficient non-volatile storage to store the unique value itself. Instead, the unique value is stored in the processing system memory in such a way that the stored unique value does not create a unique identifier for the processing system or the device. A pseudo-randomly or randomly generated initialization vector may be used to vary an encrypted data structure used to store the unique value in the memory.