DR. ALBERT YA-PO WU, M.D., PH.D.
Medical Practice at Gustave L Levy Pl, New York, NY

7820493, Oct 26, 2010

Feb 4, 2008

12/012724

Chuan-Cheng Cheng - Fremont CA, US
Shuhua Yu - Cupertino CA, US
Roawen Chen - San Jose CA, US
Albert Wu - Palo Alto CA, US

Marvell International Ltd. - Hamilton

H01L 27/10, H01L 21/8239

438132, 438129, 438215, 438281, 438601, 257209, 257529, 257E2315

A fuse structure, an integrated circuit including the structure, and methods for making the structure and (re)configuring a circuit using the fuse. The fuse structure generally includes (a) a conductive structure with at least two circuit elements electrically coupled thereto, (b) a dielectric layer over the conductive structure, and (c) a first lens over both the first dielectric layer and the conductive structure configured to at least partially focus light onto the conductive structure. The method of making the structure generally includes the steps of (1) forming a conductive structure electrically coupled to first and second circuit elements, (2) forming a dielectric layer thereover, and (3) forming a lens on or over the dielectric layer and over the conductive structure, the lens being configured to at least partially focus light onto the conductive structure. The method of (re)configuring a circuit generally includes the steps of (i) irradiating at least one lens on or near a surface of the circuit sufficient to electrically disconnect a corresponding first fuse positioned under the lens and disable a first configuration of the circuit, and (ii) irradiating at least one other lens on or near the surface of the circuit sufficient to electrically disconnect a corresponding second fuse positioned under that lens and enable a second configuration of the circuit. The structure and methods advantageously provide fuse structures having improved reliability and smaller chip area, thereby increasing the yield of the manufacturing process and the numbers of die per wafer (both gross and good).

7939445, May 10, 2011

Mar 14, 2008

12/049229

Pantas Sutardja - Los Gatos CA, US
Albert Wu - Palo Alto CA, US
Winston Lee - Palo Alto CA, US
Peter Lee - Fremont CA, US
Chien-Chuan Wei - Sunnyvale CA, US
Runzi Chang - San Jose CA, US

Marvell International Ltd. - Hamilton

H01L 21/4763

438618, 438669, 438734, 257E21575

Methods and structures for interconnects in semiconductor devices are described. A method of forming a mask pattern for a metal layer in an interconnect can include searching a layout for a metal feature with a predetermined size and an interconnect layer aligned thereto, removing the metal feature from the layout to form a modified layout, and reforming the mask pattern using the modified layout. The metal interconnect may include a first pattern of metal lines, each having a minimum feature size in a layout view in no more than one dimension; a dielectric layer on or over the first pattern of metal lines, having a substantially planar horizontal upper surface; and vias or contacts in the dielectric layer, the vias or contacts contacting a top surface of the first pattern of metal lines and a top surface of silicon structures, vias, or contacts below the first pattern of metal lines.

2011016, Jul 14, 2011

Nov 10, 2010

12/943673

Albert Wu - Palo Alto CA, US

H01L 23/498, H01L 21/768

257738, 438118, 257E21589, 257E23069

Embodiments of the present disclosure provide a method comprising forming an electrically conductive structure on a surface of a semiconductor die, attaching the semiconductor die to a substrate, forming a molding compound to encapsulate the semiconductor die, forming an opening in the molding compound, the opening to at least partially expose the electrically conductive structure, and electrically coupling a passive component to the electrically conductive structure through the opening in the molding compound. Other embodiments may be described and/or claimed.

8471376, Jun 25, 2013

May 6, 2010

12/774908

Albert Wu - Palo Alto CA, US

Marvell International Ltd. - Hamilton

H01L 23/52

257686, 257698, 257774, 257E23141, 257E23011, 257E21705, 438109

Embodiments of the present disclosure provide a substrate, one of either a semiconductor die or an interposer disposed on the substrate, the semiconductor die or the interposer having a first surface attached to the substrate and a second surface that is opposite to the first surface, one or more interconnect structures formed on the second surface of the semiconductor die or the interposer, a mold compound formed to substantially encapsulate the semiconductor die or the interposer, and one or more vias formed in the mold compound to facilitate coupling the one or more interconnect structures with another component. Other embodiments may be described and/or claimed.

2014004, Feb 13, 2014

Aug 8, 2013

13/962731

- St. Michael, BB
Albert Wu - Palo Alto CA, US
Hyun J. Shin - Palo Alto CA, US

Marvell World Trade Ltd. - St. Michael

H05K 3/00, H05K 1/18

174260, 29841

In an embodiment, there is provided a method of creating a package, the method comprising: providing an initial substrate, wherein the initial substrate comprises a carrier foil, a functional copper foil, and an interface release layer between the carrier foil and the functional copper foil; building up copper portions on the functional copper foil; attaching a chip to a first copper portion; coupling the chip to a second copper portion; encapsulating at least the chip and the copper portions with a mold; and removing the carrier foil and interface release layer.

7622731, Nov 24, 2009

Feb 22, 2007

11/709631

Pantas Sutardja - Los Gatos CA, US
Albert Wu - Palo Alto CA, US

Marvell World Trade Ltd - St. Michael

H01L 47/00

257 5, 257536, 365148

A circuit comprises a bulk silicon integrated circuit (IC). A first metallization layer is arranged adjacent to said bulk silicon IC. Phase change memory (PCM) is arranged adjacent to said first metallization layer and comprises a plurality of PCM cells each including a phase-change material, a heater that selectively heats said phase-change material, and a diode in series with said phase-change material.

8241993, Aug 14, 2012

Jul 10, 2008

12/171173

Albert Wu - Palo Alto CA, US
Runzi Chang - San Jose CA, US

Marvell World Trade Ltd. - St. Michael

H01L 21/76

438425, 438424, 438445, 438701, 257E21267, 257E21284

Methods for rounding the bottom corners of a shallow trench isolation structure are described herein. Embodiments of the present invention provide a method comprising forming a first masking layer on a sidewall of an opening in a substrate, removing, to a first depth, a first portion of the substrate at a bottom surface of the opening having the first masking layer therein, forming a second masking layer on the first masking layer in the opening, and removing, to a second depth, a second portion of the substrate at the bottom surface of the opening having the first and second masking layers therein. Other embodiments also are described.