ALBERT WANG, M.D.
Osteopathic Medicine at Kearney St, Fremont, CA

2008024, Oct 2, 2008

Jun 9, 2008

12/135502

Earl A. Killian - Altos Hills CA, US
Richardo E. Gonzalez - Menlo Park CA, US
Ashish B. Dixit - Mountain View CA, US
Monica Lam - Menlo Park CA, US
Walter D. Lichtenstein - Belmont MA, US
Christopher Rowen - Santa Cruz CA, US
John C. Ruttenberg - Newton MA, US
Robert P. Wilson - Palo Alto CA, US
Albert Ren-Ru Wang - Fremont CA, US
Dror Eliezer Maydan - Palo Alto CA, US

G06F 9/44

717100

An automated processor design tool uses a description of customized processor instruction set extensions in a standardized language to develop a configurable definition of a target instruction set, a Hardware Description Language description of circuitry necessary to implement the instruction set, and development tools such as a compiler, assembler, debugger and simulator which can be used to develop applications for the processor and to verify it. Implementation of the processor circuitry can be optimized for various criteria such as area, power consumption, speed and the like. Once a processor configuration is developed, it can be tested and inputs to the system modified to iteratively optimize the processor implementation. By providing a constrained domain of extensions and optimizations, the process can be automated to a high degree, thereby facilitating fast and reliable development.

5579510, Nov 26, 1996

Jul 21, 1993

8/095627

Albert R. Wang - Fremont CA
Richard Rudell - Los Gatos CA

Synopsys, Inc. - Mountain View CA

G06F 1700

395500

A universal synchronization element is used in a static timing verification system to represent selected combinational primitive elements, synchronous primitive elements and external primitive elements in the user's synchronous digital circuit. Each of these digital circuit element in a user's digital circuit design is represented by a corresponding universal synchronization element having a propagation time characteristic equivalent to the digital circuit element and a stable time characteristic equivalent to the digital circuit element. The propagation and stable time characteristics are defined in relation to a clock signal for the digital circuit element in the user's circuit that the universal synchronization element represents. The universal synchronization element does not a fixed timing relationship between the signals on its input and output terminals. The adjustment of stable interval starting and end times and the propagation interval starting and end times is sufficient to represent the timing characteristics of circuit element with the universal synchronization element of this invention.

6167561, Dec 26, 2000

Jun 8, 1998

9/093714

Benjamin Chen - Belmont CA
Peter Macliesh - Sunnyvale CA
Albert Wang - Fremont CA

Synopsis, Inc. - Mountain View CA

G06F 1750

716 18

A method and apparatus providing a graphical user interface (GUI) that automatically determines timing groups and path groups for a circuit representation. In a first GUI display level, the GUI displays each path group in the circuit and allows the user to change the timing constraints for each path group. In addition, the GUI indicates whether each timing group is activated by a rising or falling clock signal. In addition, the user can define subpaths of a path group. After timing analysis software has analyzed the circuit, by clicking on a timing group in the first GUI display level, the user can view a second GUI display level, which shows details of the paths in the indicated timing group. By clicking on a path in the second GUI display level, the user can view a third GUI display level, which shows a list of each of the elements in the indicated path.

7020854, Mar 28, 2006

Jul 2, 2004

10/884590

Earl A. Killian - Los Altos Hills CA, US
Ricardo E. Gonzalez - Menlo Park CA, US
Ashish B. Dixit - Mountain View CA, US
Monica Lam - Menlo Park CA, US
Walter D. Lichtenstein - Belmont MA, US
Christopher Rowen - Santa Cruz CA, US
John C. Ruttenberg - Newton MA, US
Robert P. Wilson - Palo Alto CA, US
Albert Ren-Rui Wang - Fremont CA, US
Dror Eliezer Maydan - Palo Alto CA, US

Tensilica, Inc. - Santa Clara CA

G06F 17/50, G06F 15/00

716 1, 716 18, 712 1, 712 32, 712 35, 712 36, 712200

An automated processor design tool uses a description of customized processor instruction set extensions in a standardized language to develop a configurable definition of a target instruction set, a Hardware Description Language description of circuitry necessary to implement the instruction set, and development tools such as a compiler, assembler, debugger and simulator which can be used to develop applications for the processor and to verify it. Implementation of the processor circuitry can be optimized for various criteria such as area, power consumption, speed and the like. Once a processor configuration is developed, it can be tested and inputs to the system modified to iteratively optimize the processor implementation. By providing a constrained domain of extensions and optimizations, the process can be automated to a high degree, thereby facilitating fast and reliable development.