ALBERT WAI-TUCK CHAN, MD
Medical Practice in Los Angeles, CA

6592943, Jul 15, 2003

Jan 8, 2001

09/757057

Albert W. Chan - San Jose CA
Michael G. Lee - San Jose CA
Theresa M. Larson - Hayward CA

Fujitsu Limited - Kawasaki

B05D 132

427282, 427 96, 4273761, 228 39

A method of depositing solder on a conductive region of a substrate comprising providing a substrate having a substrate aperture and a coefficient of thermal expansion. A polymeric stencil is also provided such as to have a stencil aperture and a coefficient of thermal expansion which is approximately equal to the coefficient of thermal expansion of the substrate. The method also includes disposing the polymeric stencil on the substrate such that the stencil aperture is aligned with a conductive region; and reflowing the solder paste while the polymeric stencil remains disposed on the substrate. The polymeric stencil is then removed from the substrate essentially without any solder-paste being removed with the polymeric stencil. A method of forming a polymeric stencil for solder-paste printing comprising forming in a polymeric sheet of plurality of apertures having wrinkles in the polymeric sheet in proximity to the plurality of apertures, and compressing opposing surfaces of the apertured polymeric sheet toward each other. The compressed apertured polymeric sheet is then heated and rapidly cooled to remove wrinkles in proximity to the apertures.

4654830, Mar 31, 1987

Nov 27, 1984

6/675379

H. T. Chua - Los Altos Hills CA
Cyrus Tsui - San Jose CA
Albert Chan - San Jose CA
Gary Gouldsberry - San Jose CA

Monolithic Memories, Inc. - Santa Clara CA

G11C 1300

365200

Means are provided for replacing a defective row (or column) of memory in a fuse-array PROM which comprises disabling the defective row and programming a redundant row to respond to the address of the defective row. Means are also provided for reducing the swing between high and low address voltages. The redundant row is connected via an AND gate through fuses to all ADDRESS and ADDRESS lines of the address buffer, so that the redundant row is always off until programmed. If a defective row is found, all memory cells in the defective row are disabled and the redundant row is programmed by selectively blowing fuses leading to the ADDRESS and ADDRESS lines thus causing the redundant row to respond to the address of the defective row.

4634898, Jan 6, 1987

Nov 22, 1983

6/554474

Gary Gouldsberry - San Jose CA
Albert Chan - San Jose CA
Cyrus Tsui - San Jose CA
Mark Fitzpatrick - San Jose CA

Monolithic Memories, Inc. - Santa Clara CA

H03K 19013, H03K 19088, H03K 1704, H03K 1760

307456

A unique double inversion buffer has a first means to invert and isolate the digital input signal, a second means to reinvert and further isolate the input signal, and an output means including an output transistor 94. The double inversion buffer is configured with active pull-down means on the output transistor 92. The high-to-low propagation delay time and the low-to-high propagation delay times through the double inversion buffer and reduced by use of the active pull-down means. Rapid turnoff of the output transistor is accomplished by coupling a transistor to its base to instantaneously turn it off. In a preferred embodiment, a clamping circuit 201 is used to hold the output voltage at a maximum predetermined level to further reduce the time it takes to reduce the output voltage to the logical "0" state.

4684830, Aug 4, 1987

Mar 22, 1985

6/715214

Cyrus Tsui - San Jose CA
Andrew K. L. Chan - Milpitas CA
Albert Chan - San Jose CA
Mark E. Fitzpatrick - San Jose CA
Zahid Ansari - Sunnyvale CA

Monolithic Memories, Inc. - Santa Clara CA

H03K 1920, H04A 900

307465

An output circuit (50) is provided for a programmable logic array (PLA) integrated circuit. The output circuit (50) includes a flip flop (52) which stores a given output term from the array. The flip flop (52) contains a set input lead (S) and a reset input lead (R). The signals present at the set input, reset input, the clock leads are generated by programmable logic within the PLA. A multiplexer (54) is provided which receives the output data of the flip flop (52) and the signal constituting the input data for the flip flop. The multiplexer provides the data input signal on the multiplexer output lead (60) when both the set and reset input signals are true. However, if either or both the set and reset input signals are false, then the multiplexer (54) provides the Q output signal from the flip flop (52) on the multiplexer output lead (60). The multiplexer output signal is presented to a three-state buffer (62) which in turn drives an output pin.

4701695, Oct 20, 1987

Feb 14, 1986

6/829260

Albert Chan - San Jose CA
Mark Fitzpatrick - San Jose CA
Don Goddard - Cupertino CA
Robert J. Bosnyak - Los Gatos CA
Cyrus Tsui - San Jose CA

Monolithic Memories, Inc. - Santa Clara CA

G01R 3102, G06F 1100

324510

Test circuitry is included in a PROM memory for detecting shorts between bit lines and word lines and shorts or leaks in a memory cell. The circuitry enables a selected positive voltage to be applied across all memory cells in the memory so that the existence of leaky memory cells or shorts in the memory can be detected during testing. The test circuitry has no appreciable effect on the memory during normal operation of the memory.

4670708, Jun 2, 1987

Jul 30, 1984

6/635861

Bob Bosnyak - Palo Alto CA
Albert Chan - San Jose CA
Mark Fitzpatrick - San Jose CA
Gary Gouldsberry - San Jose CA
Cyrus Tsui - San Jose CA
Andrew K. Chan - Milpitas CA

Monolithic Memories, Inc. - Santa Clara CA

G01R 3102

324 51

Circuitry is provided for testing fusible link arrays for short circuits around the fusible links. Each link is electrically isolated and compared with a pair of reference fusible links to detect the presence or absence of a short circuit.

4625311, Nov 25, 1986

Jun 18, 1984

6/621536

Mark E. Fitzpatrick - San Jose CA
Cyrus Y. Tsui - San Jose CA
Andrew K. Chan - Milpitas CA
Albert L. Chan - San Jose CA

Monolithic Memories, Inc. - Santa Clara CA

G01R 1512

371 15

A field programmable array logic circuit is described wherein existing sensing circuitry is employed along with circuitry to enable every fuse location to be isolated, so that both a. c. and verification testing takes place under the same conditions, i. e. voltage levels and frequency, which occurs during normal operation of the programmed circuit.

2005005, Mar 17, 2005

Sep 15, 2003

10/663207

Albert Chan - San Jose CA, US

B32B031/26

156307700, 252519330

A thermally conductive interface adhesive for attaching an electronic component, such as an integrated circuit chip, to a heat receiving substrate, such as a heat spreader, is disclosed. The interface adhesive comprises a mixture of solder powder, flux and a curable polymer, such as an epoxy, which form a paste. Preferably, the interface adhesive further comprises particles of a metallic filler material, such as silver or copper. Preferably, the solder has a relatively low melting point, and the polymer is thermosetting. After the adhesive paste is applied it is processed by heating it to melt the solder after which the polymer is cured, such that a metallic network is formed within the adhesive layer. The cured adhesive layer has a thermal conductivity of about 15 W/m-K or more.