ALBERT CHAN, MD
Marriage and Family Therapists at El Camino Real, Palo Alto, CA

License number

California A74855

Professional information

Albert Chan

Position:

Chief Medical Information Officer at Palo Alto Foundation Medical Group, Medical Director, My Health Online at Sutter Physician Services, Medical Director at David Druker Center for Health Systems Innovation, Member, Clinical Solutions Advisory Board at Wolters Kluwer, Board of Directors at Los Altos Community Foundation, Family Medicine Physician and Medical Informatician at Palo Alto Foundation Medical Group

Location:

San Francisco Bay Area

Industry:

Medical Practice

Work:

Palo Alto Foundation Medical Group - Mountain View, CA since Dec 2010 - Chief Medical Information Officer Sutter Physician Services since Jan 2011 - Medical Director, My Health Online David Druker Center for Health Systems Innovation since May 2010 - Medical Director Wolters Kluwer since Jun 2011 - Member, Clinical Solutions Advisory Board Los Altos Community Foundation since Nov 2008 - Board of Directors Palo Alto Foundation Medical Group since Oct 2002 - Family Medicine Physician and Medical Informatician Palo Alto Medical Foundation Sep 2007 - Dec 2011 - Study Physician, EMPOWER-D Palo Alto Foundation Medical Group Nov 2006 - Nov 2010 - Physician Champion - EpicCare Ambulatory EHR and PAMFOnline (MyChart) California Health and Human Services Agency Dec 2009 - Mar 2010 - Co-Chair, Patient Engagement Work Group, Health Information Technology Office of the National Coordinator Health IT Extension Program: Regional Centers Feb 2010 - Feb 2010 - Grant Reviewer Certification Commission for Healthcare Information Technology Jul 2009 - Dec 2009 - Co-Chair, Personal Health Records Work Group VA Palo Alto /Stanford 2002 - 2004 - Post doctoral fellow, Medical Informatics

Education:

Stanford University School of Medicine 2002 - 2004
MS, Biomedical Informatics University of California, San Francisco - School of Medicine 2002 - 2004
University of California, San Diego - School of Medicine 1994 - 1999
MD, Medicine Peking University 1997 - 1998
Stanford University 1990 - 1994
BS, Biological Sciences Petaluma High School

Skills:

Biomedical Informatics, Health, Ambulatory, Informatics, Healthcare IT, Clinical Informatics, Healthcare Information Technology

Honor & Awards:

Silicon Valley / San Jose Business Journal Future Health Care Leader Award, 2012 Fellow, American Academy of Family Practice, 2006 NLM Informatics Training Grant, 2002-2004 First Place, UCSD School of Medicine ISP Fair (Thesis Award), 1999 Edwin Reithmayer Memorial Scholarship Award For Excellence in Undergraduate Medicine, 1999 University of California Education Abroad Scholarship, 1997 UCSD Lipton Family/Friends of the International Center Scholarship, 1997 California Academy of Family Practice Scholar, 1994 Stanford Undergraduate Teaching Award, 1993-4 Howard Hughes Research Scholar, 1993 Chevron Corporation REACH Scholar, 1990-1994 Hertz Foundation Scholar, 1990-1992

Certifications:

Epic Physician Builder Certification, Epic Systems Corporation

Sequential And Simultaneous Manufacturing Programming Of Multiple In-System Programmable Systems Through A Data Network

US Patent:

6023570, Feb 8, 2000

Filed:

Feb 13, 1998

Appl. No.:

9/023506

Inventors:

Howard Y. M. Tang - San Jose CA
Cyrus Y. Tsui - Los Altos CA
Albert Chan - Palo Alto CA

Assignee:

Lattice Semiconductor Corp. - Hillsboro OR

International Classification:

G06F 1338

US Classification:

39550018

Abstract:

An in-system programmable (ISP) system, having a plurality of ISP devices, can be programmed by remote access from a host controller. The remote access can be accomplished over a wired data network, a wireless data network such as an infra-red data network and a radio wave data network, or a hybrid network including both a wired data network portion and a wireless data network portion. An access interface connects the host controller to an ISP programmer over the wired or wireless communication link. The ISP programmer programs the ISP system in accordance with ISP programming conventions. The ISP programmer can be provided by an integrated circuit having a microprocessor core.

Integrated Programmable Logic Device With Control Circuit To Power Down Unused Sense Amplifiers

US Patent:

5138198, Aug 11, 1992

Filed:

May 3, 1991

Appl. No.:

7/695180

Inventors:

Ju Shen - San Jose CA
Albert L. Chan - Palo Alto CA
Chan-Chi J. Cheng - San Jose CA

Assignee:

Lattice Semiconductor Corporation - Hillsboro OR

International Classification:

H03K 19177

US Classification:

307465

Abstract:

A programmable logic device is disclosed which includes sense amplifiers for determining the programmed/unprogrammed state of product terms coupled to respective ones of the sense amplifiers. A control circuit is provided for the sense amplifiers to permit, under control from a control signal, disabling sense amplifiers which are not being used in the achievement of the logical function of the programmable logic device to avoid unnecessary use of current by the sense amplifiers which are not operative for the function being implemented. In addition to eliminating current drain by the unused sense amplifier, the control circuit also ensures that a low output signal will always be provided at the output of the disabled sense amplifier to avoid potentially indicating an incorrect logical output from the sense amplifier which is connected to other devices in the programmable logic device.

Multiplexed Control Pins For In-System Programming And Boundary Scan State Machines In A High Density Programmable Logic Device

US Patent:

5412260, May 2, 1995

Filed:

Aug 13, 1993

Appl. No.:

8/106263

Inventors:

Cyrus Y. Tsui - Los Altos CA
Albert L. Chan - Palo Alto CA
Kapil Shankar - Fremont CA
Ju Shen - Saratoga CA

Assignee:

Lattice Semiconductor Corporation - Hillsboro OR

International Classification:

H03K 19003

US Classification:

326 39

Abstract:

A structure and a method to implement in-system programming (ISP) and boundary-scan testing in an integrated circuit using the same pins to control both functions. The SDI, SCLK, MODE and SDO connections required for in-system programming and the TDI, TCK, TMS and TDO connections required for boundary-scan testing are multiplexed such that they are provided from the same four pins. An in-system programming enable pin is used to control the multiplexing of these pins. In an alternative embodiment, both in-system programming and boundary-scan testing are performed using the same pins and the same state machine. The test logic architecture specified in IEEE Standard 1149. 1-1990 is utilized. To implement the in-system programming instructions, the instruction register of Std. 1149. 1-1990 is modified to include private instructions which perform the desired programming functions.

Sense Amplifier With Depletion Transistor Feedback

US Patent:

5162679, Nov 10, 1992

Filed:

May 3, 1991

Appl. No.:

7/695181

Inventors:

Ju Shen - San Jose CA
Albert L. Chan - Palo Alto CA
Chan-Chi J. Cheng - San Jose CA

Assignee:

Lattice Semiconductor Corporation - Hillsboro OR

International Classification:

G01R 1900

US Classification:

307530

Abstract:

A sense amplifier circuit is disclosed which utilizes a field effect transistor having a negative threshold voltage to provide a faster switching speed for a given current consumption. A depletion mode transistor is utilized as the feedback transistor, with the gate of the depletion mode transistor being coupled to the output of the second stage of the sense amplifier. The first stage of the sense amplifier includes in addition to the depletion mode transistor a second field effect transistor connected in series with said feedback transistor, with the gate and drain of the second transistor being commonly connected. The sense amplifier circuit also includes third and fourth stages providing inversion and amplification of the signal provided at the output of the second stage, with the third and fourth stages comprising a depletion load inverter and a CMOS inverter, respectively.

Combination Of Global Clock And Localized Clocks

US Patent:

6133750, Oct 17, 2000

Filed:

Apr 27, 1998

Appl. No.:

9/069035

Inventors:

Albert Chan - Palo Alto CA
Ju Shen - San Jose CA
Cyrus Y. Tsui - Los Altos CA
Allan T. Davidson - San Jose CA

Assignee:

Lattice Semiconductor Corp. - San Jose CA

International Classification:

H03K 19177

US Classification:

326 41

Abstract:

A programmable logic device includes a global clock structure and a plurality of localized clock structures. Each localized clock structure distributes a respective localized clock signal to a corresponding portion of the programmable logic device. The global clock structure distributes a global clock signal to all portions of the programmable logic device.

Programmable Integrated Circuit Device With Slew Control And Skew Control

US Patent:

6229336, May 8, 2001

Filed:

Nov 6, 1998

Appl. No.:

9/186917

Inventors:

Bradley Felton - Devon, GB
Albert Chan - Palo Alto CA
Ju Shen - Saratoga CA
Cyrus Y. Tsui - Los Altos Hills CA
Rafael C. Camarota - Sunnyvale CA

Assignee:

Lattice Semiconductor Corporation - Hillsboro OR

International Classification:

H03K 19173, H03K 19177

US Classification:

326 38

Abstract:

A programmable integrated circuit device includes a plurality of output terminals, each output terminal for use in transmitting a respective output signal. Timing control circuitry is connected to the output terminals. The timing control circuitry is operable to delay the output signal on each output terminal and is further operable to control a slew rate of the output signal on each output terminal.

Programmable Logic Device With Enhanced Wide Input Product Term Cascading

US Patent:

6903573, Jun 7, 2005

Filed:

Jul 14, 2003

Appl. No.:

10/619711

Inventors:

Jason Cheng - Fremont CA, US
Cyrus Tsui - Los Altos Hills CA, US
Satwant Singh - Fremont CA, US
Albert Chan - Palo Alto CA, US
Ju Shen - Saratoga CA, US
Clement Lee - Portland OR, US

Assignee:

Lattice Semiconductor Corporation - Hillsboro OR

International Classification:

H03K019/177

US Classification:

326 41, 326 47

Abstract:

A programmable device with logic blocks is configured to cascade product terms from one logic block to another to increase the logical input width of the product terms. Each logic block may produce a plurality of product terms based upon the selection of inputs from a routing structure. Logic blocks configured to receive cascaded product terms includes a plurality of AND gates corresponding to the plurality of product terms.

Combination Of Global Clock And Localized Clocks

US Patent:

6191609, Feb 20, 2001

Filed:

Nov 3, 1999

Appl. No.:

9/433642

Inventors:

Albert Chan - Palo Alto CA
Ju Shen - Saratoga CA
Cyrus Y. Tsui - Los Altos CA
Allan T. Davidson - San Jose CA

Assignee:

Lattice Semiconductor Corporation - Hillsboro OR

International Classification:

H03K 19177

US Classification:

326 38

Abstract:

Output Logic Macrocell With Enhanced Functional Capabilities

US Patent:

5191243, Mar 2, 1993

Filed:

May 6, 1991

Appl. No.:

7/696907

Inventors:

Ju Shen - San Jose CA
Albert L. Chan - Palo Alto CA
Kapil Shankar - San Jose CA
Cyrus Tsui - Vancouver WA

Assignee:

Lattice Semiconductor Corporation - Hillsboro OR

International Classification:

H03K 19177

US Classification:

307465

Abstract:

An output logic macrocell ("OLMC") containing an exclusive OR gate is associated with the product terms and other outputs of a logic block such as a programmable logic array. The OLMC is capable of providing enhanced functions, including cascaded exclusive OR gates, function sharing, T and J-K flip-flop emulation, asynchronous clocking, and a reset selection. In addition, a logic block is used as the source of an asynchronous clock pulse and is connected to the global clock distribution system of a device such as a high density programmable logic device.