ABDALLAH MAHMOUD ITANI
Pilots at Cindy Ln, Ballston Spa, NY

License number
New York A2403259
Issued Date
Jul 2016
Expiration Date
Jan 2017
Category
Airmen
Type
Authorized Aircraft Instructor
Address
Address
612 Cindy Ln, Ballston Spa, NY 12020

Professional information

Abdallah Itani Photo 1

Pulse Modulated Electronic Voltage Controller With Smooth Voltage Output

US Patent:
4408268, Oct 4, 1983
Filed:
Aug 9, 1982
Appl. No.:
6/406651
Inventors:
Philip H. Peters - Greenwich NY
Abdallah M. Itani - Ballston Spa NY
Assignee:
General Electric Company - Schenectady NY
International Classification:
H02M 302, H02M 502
US Classification:
363 62
Abstract:
Four switching elements are configured to reduce the voltage of either an alternating or a direct current electrical power source. The present circuit effectively operates like a variable autotransformer when used with a. c. input power. Additionally, when employed with a conventional resistive load, the present invention exhibits a power factor near unity.


Abdallah Itani Photo 2

Driver Circuit Controller For Ac To Ac Converters

US Patent:
4613795, Sep 23, 1986
Filed:
Jun 24, 1985
Appl. No.:
6/748076
Inventors:
Abdallah M. Itani - Ballston Spa NY
Victor D. Roberts - Burnt Hills NY
Assignee:
General Electric Company - Schenectady NY
International Classification:
H05B 3700
US Classification:
315205
Abstract:
The switches of an AC to AC converter are switched synchronously with the AC supply voltage. EMI conducted to the AC power line is greatly reduced since the rectifier diodes are off at the time of switching, thus avoiding undesirable effects on nearby electrical apparatus. The converter is useful in a ballast for a discharge lamp.


Abdallah Itani Photo 3

Turbo Decoder Control For Use With A Programmable Interleaver, Variable Block Length, And Multiple Code Rates

US Patent:
6516437, Feb 4, 2003
Filed:
Mar 7, 2000
Appl. No.:
09/519903
Inventors:
Nick Andrew Van Stralen - Schenectady NY
Stephen Michael Hladik - Albany NY
Abdallah Mahmoud Itani - Ballston Spa NY
Robert Gideon Wodnicki - Schenectady NY
John Anderson Fergus Ross - Del Mar CA
Assignee:
General Electric Company - Niskayuna NY
International Classification:
H03M 1327
US Classification:
714755, 714786
Abstract:
A turbo decoder control comprises an address generator for addressing systematic data, parity data, and systematic likelihood ratios according to a pre-determined memory mapping. The systematic data samples are accessed in the order required by the MAP decoding algorithm such that interleaving and de-interleaving functions in the MAP decoding algorithm are performed in real-time, i. e. , without delay. Such memory-mapping in combination with data handling functions (e. g. , multiplexing and combinatorial logic) minimizes memory requirements for the turbo decoder and allows for use of programmable interleavers, variable block lengths, and multiple code rates.


Abdallah Itani Photo 4

Modular Turbo Decoder For Expanded Code Word Length

US Patent:
6594792, Jul 15, 2003
Filed:
Apr 28, 2000
Appl. No.:
09/561333
Inventors:
Stephen Michael Hladik - Albany NY
Abdallah Mahmoud Itani - Ballston Spa NY
Nick Andrew Van Stralen - Ballston Spa NY
Robert Gideon Wodnicki - Schenectady NY
John Anderson Fergus Ross - Del Mar CA
Assignee:
General Electric Company - Niskayuna NY
International Classification:
H03M 1329
US Classification:
714755, 714780, 714794
Abstract:
A turbo decoder system utilizing a MAP decoding algorithm has a predetermined number of turbo decoder modules for decoding segments of a turbo code component code word in parallel, thereby expanding the block-length and data-rate capability of the turbo decoder system. Input data samples are provided to an interleaver/de-interleaver module wherein they are divided into segments of predetermined size, each segment being provided to a respective turbo decoder module. The outputs of each turbo decoder module are a posteriori probabilities which are re-ordered in the interleaver/de-interleaver module, segmented, and provided back to the turbo decoders as a priori information-bit probabilities. For the case of a turbo code comprising two component codes, the a posteriori information-bit probabilities are re-ordered according to the interleaver definition at the end of odd-numbered half iterations, while at the end of even-numbered half iterations, they are re-ordered according to the de-interleaver definition. Decoding continues until the desired number of iterations have been performed. Data decisions are made on the final a posteriori bit probability estimates.


Abdallah Itani Photo 5

Protection Arrangement For Switching Device Of A Capacitive Load Pulser Circuit

US Patent:
4680533, Jul 14, 1987
Filed:
Aug 1, 1985
Appl. No.:
6/761459
Inventors:
Abdallah M. Itani - Ballston Spa NY
Gerald J. Carlson - Scotia NY
Peter W. Dietz - Greenwich NY
Assignee:
General Electric Company - Schenectady NY
International Classification:
B03C 301
US Classification:
323240
Abstract:
A method and apparatus for protecting switching elements, and in particular, thyristor switching elements, which are used to supply pulses to a capacitive load, from damage resulting from sparkover occurring in that load are described. The load voltage pulse is characterized by a period of rising voltage followed by a period of falling voltage, these two periods being separated by a transition period of maximum vulnerability of the switching element to damage from sparkover. Specifically, during this period of maximum vulnerability of the switching elments to damage, a gate trigger pulse is applied to the elements to cause them to resume a conductive state, independent of the occurrence of an abnormal sparkover condition.


Abdallah Itani Photo 6

Data Transmission System And Method

US Patent:
4393516, Jul 12, 1983
Filed:
Mar 9, 1979
Appl. No.:
6/019114
Inventors:
Abdallah M. Itani - Ballston Spa NY
Assignee:
Electric Power Research Institute, Inc. - Palo Alto CA
International Classification:
H04B 900
US Classification:
455608
Abstract:
A data transmission system and method is provided for transferring digital information which has been converted to a multiframe format of serial bits over a single optical cable. The mutliframe format used by the system includes sequential data frames each containing a sequence of bits at a bit frequency, of which a certain number are data bits containing the digital information. The data frames are transferred by way of the optical cable to a receiver. In the receiver a clock signal is generated by a variable oscillator which operates at a frequency substantially equal to the bit frequency. Circuitry responsive to the bits maintains a predetermined phase relationship between the clock signal from the oscillator and the bits. Decoder circuitry receives the transmitted bits and decodes the bits to retrieve the digital information using the clock signal from the oscillator. The method of retrieving the digital information from the above-described multiframe format, after having been transferred over the single optical cable, includes the following steps: A clock signal is generated having a frequency substantially equal to the bit frequency.


Abdallah Itani Photo 7

False Triggering Protection For Switching Device Of A Capacitive Load Pulser Circuit

US Patent:
4680532, Jul 14, 1987
Filed:
Aug 1, 1985
Appl. No.:
6/761458
Inventors:
Abdallah M. Itani - Ballston Spa NY
Peter W. Dietz - Greenwich NY
Gerald J. Carlson - Scotia NY
Assignee:
General Electric Company - Schenectady NY
International Classification:
B03C 301
US Classification:
323240
Abstract:
A method and apparatus for protecting switching elements, and in particular, thyristor switching elements, which are used to supply pulses to a capacitive load, from damage resulting from false triggering signals, i. e. , triggering signals not accompanied by actual sparkover conditions in the load. Since termination of normal pulse cycles in such pulser systems are accomplished by a return to high forward voltage across the switching elements, false triggers generated closely prior to such termination and within the forward recovery time of a thyristor switching element present a danger that the termination of a normal cycle will result in a weak turn-on and consequent damage of the switching element. By insuring that all such potentially false triggers have a duration which extends past termination of the pulse cycle damage to the switching element resulting from such false triggers is inhibited.


Abdallah Itani Photo 8

System For Reading Magnetic Sensors For Fault Location In Gas-Insulated Electrical Apparatus

US Patent:
4475078, Oct 2, 1984
Filed:
Dec 22, 1980
Appl. No.:
6/218503
Inventors:
Abdallah M. Itani - Ballston Spa NY
Assignee:
Electric Power Research Institute, Inc. - Palo Alto CA
International Classification:
G01R 3108, G01R 33025, G01R 3304
US Classification:
324 52
Abstract:
A fault location system for use with sealed, gas-insulated electrical power apparatus. The system includes a sensor for placement in close proximity to the outer surface of a housing of the apparatus and a detector for in-place reading of the sensor. The detector comprises a first fluxgate magnetometer for detecting magnetization of the sensor. A second fluxgate magnetometer is positioned adjacent and parallel to the first magnetometer to detect only the background magnetic field. An alternating current electrical signal is applied to the magnetometers. A direct current is then automatically generated wherein the direct current is a function of the even harmonics of the ac output of the second magnetometer. The direct current is used to cancel the effects of the background magnetic field detected by the second magnetometer. As such, the direct current is applied to the first magnetometer to cancel the effects of the background magnetic field therefrom.


Abdallah Itani Photo 9

High-Speed Turbo Decoder

US Patent:
6304996, Oct 16, 2001
Filed:
Mar 8, 1999
Appl. No.:
9/263566
Inventors:
Nick Andrew Van Stralen - Schenectady NY
John Anderson Fergus Ross - Schenectady NY
Stephen Michael Hladik - Albany NY
Abdallah Mahmoud Itani - Ballston Spa NY
Robert Gideon Wodnicki - Schenectady NY
Assignee:
General Electric Company - Schenectady NY
International Classification:
H03M 1303
US Classification:
714796
Abstract:
A high-speed turbo decoder utilizes a MAP decoding algorithm and includes a streamlined construction of functional units, or blocks, amenable to ASIC implementation. A gamma block provides symbol-by-symbol a posteriori state transition probability estimates. Two gamma probability function values are provided via selection switches to the alpha and beta blocks for calculating the alpha and beta probability function values, i. e. , performing the alpha and beta recursions, respectively, in parallel, thus significantly increasing decoding speed. A scaling circuit monitors the values of the alpha and beta probability functions and prescribes a scale factor such that all such values at a trellis level remain within the precision limits of the system. A sigma block determines the a posteriori state transition probabilities (sigma values) and uses the sigma values to provide soft-decision outputs of the turbo decoder.


Abdallah Itani Photo 10

Methods And Apparatus For Generating Test Vectors And Validating Asic Designs

US Patent:
5920830, Jul 6, 1999
Filed:
Jul 9, 1997
Appl. No.:
8/890273
Inventors:
William Thomas Hatfield - Schenectady NY
Abdallah Mahmoud Itani - Ballston Spa NY
William Macomber Leue - Albany NY
Assignee:
General Electric Company - Schenectady NY
International Classification:
G01R 3128, G06F 945, G06F 9455
US Classification:
702119
Abstract:
Methods and apparatus for generating test vectors for use in testing ASIC designs at both the functional and circuit levels, and for comparing the results of functional level and circuit level tests, employ a set of software tools to facilitate generating test vectors and to compare results of simulation at the functional level with results of simulation at the synthesized circuit level. The software tool set includes a preprocessor program which reads source files and produces skeleton test vector files, a compiler program for compiling the test vector files, and an output comparison program for comparing functional level test results with circuit simulation level test results.